发明名称 |
METHOD FOR MANUFACTURING MULTILAYERED INTERCONNECTION |
摘要 |
PURPOSE: A method for manufacturing a multilayered interconnection is provided to eliminate the need of overlap margin of an interconnection hole between upper and lower interconnections and to form a plurality of interconnections in a small region in a layout process, by forming an interconnection material while considering the interconnections. CONSTITUTION: The first insulating layer(24) is formed which has a contact hole exposing a partial surface of a source/drain region(23). The first interconnection material having a predetermined thickness is deposited on the entire surface including the contact hole. The first interconnection material is selectively patterned to form an interconnection(27). A predetermined region of the first interconnection material excluding the interconnection is selectively patterned to form the first interconnection(28). The second insulating layer(29) is deposited on the entire surface including the interconnection. The second insulating layer is planarized to expose the surface of the interconnection. The second interconnection material is deposited on the exposed interconnection and the second insulating layer, and the second interconnection material is selectively patterned to form the second interconnection(30).
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申请公布号 |
KR20010027592(A) |
申请公布日期 |
2001.04.06 |
申请号 |
KR19990039393 |
申请日期 |
1999.09.14 |
申请人 |
HYUNDAI MICRO ELECTRONICS CO., LTD. |
发明人 |
KIM, HONG SEON;NAM, SANG HYEOK |
分类号 |
H01L21/786;(IPC1-7):H01L21/786 |
主分类号 |
H01L21/786 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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