| 摘要 |
<p>PROBLEM TO BE SOLVED: To solve a problem that a storage data amount of a FIFO many not accurately be monitored in the case that a write clock and a read clock of the FIFO have the same speed but are asynchronously with each other. SOLUTION: A write counter 1 generates a write address 10 of the FIFO synchronously with a write clock 7 and a read counter 2 generates a read address 14 of the FIFO synchronously with a read clock 9 in a form of gray codes respectively. A slip decision circuit 3 receives the write address, the read clock and a corrected write address 13 to discriminate whether or not a signal resulting from retiming the write address by the read clock is slipped. A slip correction circuit 4 receives an output of the slip discrimination circuit 3 and the read clock to provide an output of the corrected write address on the occurrence of a slip on the basis of a slip decision signal 12 outputted from the slip discrimination circuit. A storage data amount decision circuit 5 receives the write address and the read address and provides an output of a detection signal 15 when the stored data amount reaches a prescribed amount.</p> |
