发明名称 DISTRIBUTED DATA PROCESSOR
摘要 <p>PURPOSE:To simultaneously impart clock signals to all processing elements and to enable respective processing elements to simultaneously read an asynchronism requiring signal from a host unit by providing the delay means of the clock signal and a delay time deciding means on a distributed data processor consisting of plural processing elements. CONSTITUTION:An asynchronism requirement arbitrating means 24 receives the asynchronism requiring signal from host CPU 20, gives the instruction of the deceleration and acceleration of an MPU clock for an MPU clock generation means 23 and issues the received asynchronism requiring signal to processors 22. A clock distribution means 26 is provided with a delay switching means 25, delays the MPU clock through a propagation time counting means 27 while distributing it to respective processors 22 in accordance with the delay function. Thus, the processors 22 simultaneously receive the asynchronism requiring signal of an interruption requiring signal from host CPU 20 in accordance with the same clock signal and execute a data processing.</p>
申请公布号 JPH0460742(A) 申请公布日期 1992.02.26
申请号 JP19900171069 申请日期 1990.06.28
申请人 FUJITSU LTD 发明人 YOSHIZAWA HIDEKI;KATO HIDEKI;ICHIKI HIROMOTO;MASUMOTO DAIKI
分类号 G06F15/16;G06F1/10;G06F9/52;G06F15/177;G06F15/80 主分类号 G06F15/16
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