发明名称 DEVICE AND METHOD FOR CONTROLLING PIPELINE WRITE/READ OF TRANSMISSION SYSTEM USING DMA LOGIC
摘要 PURPOSE: The device and the method is provided to control the data transmission between the internal RAM and the external memory by a hardware while transmitting the data between the host and the internal RAM. CONSTITUTION: The device comprises a host interface controller(100), a pipeline write/read controller(120), a memory controller(140), an inner memory controller(150), and an inner memory(160). The host interface controller controls the interface which sends/receives the data with the external host. The pipeline write/read controller controls to operate the pipeline write/read or the DMA by responding to the CONS. The DMA controller(124) controls to prevent the miss operation due to the data transmission speed gap by counting the data transmission volume of the DMA0(122) and of the DMA1. The inner memory controller, which is connected between the inner memory and the DMA0 and the DMA1, controls the data transmission between the inner memory and the host or between the external memory and the inner memory. The inner memory can be implemented by the RAM and the external memory can be implemented by the flash memory. The memory controller controls the data transmission between the inner memory and the external memory.
申请公布号 KR20010026743(A) 申请公布日期 2001.04.06
申请号 KR19990038170 申请日期 1999.09.08
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KANG, JEONG SEON
分类号 G06F13/16;(IPC1-7):G06F13/16 主分类号 G06F13/16
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