| 摘要 |
<p>PROBLEM TO BE SOLVED: To perform the erocetta sine casella operation and sum and difference operation contained in DCT/IDCT. SOLUTION: A product sum operating processor 12 is connected to an RISC processor 10 and the processor 10 executes DCT/IDCT operation for the compression/expansion of image signals and voice signals. At the time of performing erocetta sine casella operation and sum and difference operation, the processor 10 issues a register wire instruction and writes data to be operated in the input registers 34 and 36 of a processor 12, executes the erocetta sine casella operation or sum and difference operation by using the written data to be operated, and writes the operated results in an output register 42. The results of the erosetta sine casella operation or sum and difference operation written in the register 42 are read out in accordance with a register readout instruction from the RISC processor 10.</p> |
