| 摘要 |
PURPOSE: A method for manufacturing a gate electrode of a complementary-metal-oxide-semiconductor(CMOS) transistor is provided to optimize the thickness of a spacer of an N-type metal-oxide-semiconductor(NMOS) and a P-type metal-oxide-semiconductor(PMOS), by doping n+ type impurities into a source/a drain and a polysilicon layer of the NMOS transistor while doping p+ type impurities into a polysilicon layer of the PMOS transistor. CONSTITUTION: A gate oxide layer, a polysilicon layer and a boron silicate glass(BSG) layer are formed on a substrate(20) having an N-well(21A) and a P-well(21B). The BSG layer is selectively etched to form a gate of N-type metal-oxide-semiconductor(NMOS) transistor and a P-type metal-oxide-semiconductor(PMOS) region. The first nitride layer spacer(26) is formed on the entire structure, and the BSG layer in the gate region of the NMOS transistor is etched. A phosphorous silicate glass(PSG) layer(27) is formed on the entire structure. The PSG layer is selectively etched to form a gate electrode of the a PMOS region, a NMOS transistor region and the second nitride spacer. After a diffusion process is performed, boron is doped into the gate electrode of the PMOS transistor while phosphor is doped into the gate electrode and a source/drain region of the NMOS transistor.
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