CIRCUIT FOR GENERATING ADDRESS AND FOR DECODING WITH SCHEME OF SINGLE AND DOUBLE DATA RATES WITHIN HIGH-SPEED RANDOM ACCESS MEMORY DEVICE

摘要

PURPOSE: A circuit for generating address and for decoding is provided to automatically generate sequential burst addresses within a high-speed random access memory device CONSTITUTION: The circuit(100) includes an address buffer(110) an address generator(120), a predecoder(130) and a decoder(140). Address bit signals(XA2-XAn) except initial address bit signals(XA0,XA1) of a multi-bits address(XA0-XAn) input to the address buffer(110). The initial address bit signals(XA0,XA1) input to the address generator(120) which is drived by the first and second clock signals. The address generator(120) generates sequential burst addresses(B0,B1) according to control signals(MODE,/DDR). The first control signal(MODE) informs a sequential burst mode or an interleaved burst mode. Also, the second control signal(/DDR) informs a SDR(Single Data Rate) mode or a DDR(Double Data Rate) mode. The sequential burst addresses(B0,B1) are decoded by the predecoder(130) and decoder(140).