REDUNDANCY DECODER OF SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A redundancy decoder of a semiconductor memory device is provided to reduce a current flowing from a supply voltage to a ground by using an ATD(Address Transition Detection) pulse generated whenever an external address(or data) transits. CONSTITUTION: The redundancy decoder includes a selective pull-up/pull-down portion(20), a selective pull-down portion(30), an ATD pulse inverting portion(60), a selective latch portion(70) and a redundancy cell driving signal generator(40). The selective pull-up/pull-down portion pulls up a reference node when a redundancy decoder enable signal, a chip selection signal and the ATD pulse are enabled, and pulls down the reference node when the chip selection signal is disabled. The selective pull-down portion has a plurality of fuses selectively cut according to address signals of predetermined failed memory cells when a master fuse is cut, maintains a voltage level of the reference node pulled up by the selective pull-up/pull-down portion when the address signals of the predetermined failed memory cells are applied in a state that the fuses are cut, and pulls down the reference node when the other address signals except the address signals of the predetermined failed memory cells are applied. The ATD pulse inverting portion inverts the ATD pulse. The selective latch portion latches the voltage of the reference node when the ATD pulse and an inverted ATD pulse are disabled, and does not latch the voltage of the reference node when the ATD pulse and the inverted ATD pulse. The redundancy cell driving signal generator generates a redundancy cell which is enabled by the pulled up voltage of the reference node latched by the selective latch portion and generates a redundancy cell driving signal activating a redundancy cell replaced with the failed memory cell.