| 摘要 |
PURPOSE: An inverter circuit is provided to equalize delay time of each inverter chain, so obtains enough margins between signals within a memory device. CONSTITUTION: The circuit includes the first and second fuse blocks(10,11), the first and second transmission gates(T1,T2), the third and fourth transmission gates(T3,T4), the first inverter-delay chain(16), the second inverter-delay chain(17) and the third inverter-delay chain(18). The first and second fuse blocks(10,11) selectively generate a cutting signal and an uncutting signal according to variation of Vcc. The first and second transmission gates(T1,T2) selectively perform switching operation according to an output signal from the first fuse block(10). The third and fourth transmission gates(T3,T4) selectively perform switching operation according to an output signal from the second fuse block(11). An input signal inputs to the first inverter-delay chain(16). Output signals from the first and second transmission gates(T1,T2) selectively input to the second inverter-delay chain(17). Output signals from the third and fourth transmission gates(T3,T4) selectively input to the third inverter-delay chain(18).
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