| 摘要 |
PURPOSE: A ferroelectric memory is provided to reduce area for forming a memory cell and to stack the memory cell area on the upper portion of a logic circuit area. CONSTITUTION: The device includes a unit cell having the MxN(M and N are an integer) arrangement, M bit lines(B0,B1,B2), N plate electrode lines(P0,P1,P2), MxN capacitors, transistors(TB0,TB1,TB2) for driving a bit line and transistor(TP0,TP1,TP2) for driving a plate electrode line. The N plate electrode lines are crossed to each of the M bit lines. The MxN capacitors are that one electrode is connected to a plate electrode line and other electrode to a bit line every points at which the bit lines and the plate electrode lines are crossed. Each of the transistors for driving bit lines is one to one connected to each of the M bit lines and selectively drives a specific bit line of the M bit lines. Each of the transistors for driving a plate electrode line is one to one connected to each of the N plate electrode lines and selectively drives a specific plate electrode line of the N plate electrode lines.
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