发明名称 SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor memory in which an access speed for a memory cell can be increased and increase in current consumption can be suppressed. SOLUTION: A memory cell array 12 comprises plural main word lines MW, plural sub-word lines SW corresponding to each main word line, and sub-word lines SW in the direction of column, and is divided into plural sub-arrays 13A-13H. The plural main word lines MW is divided into two groups of main word line groups G1 and G2. A main word decoder 14 selects one main word line MW out of the main word line groups G1, G2, plural sub-word decoders 16A-16H select sub-word lines SW corresponding to one main word line group in sub-arrays 13A-13H. Plural driving circuits 20, 22 drive correspondent sub- word line SW based on a selected result of the main word decoder 14 and the sub-word decoders 16A-16H.
申请公布号 JP2001093281(A) 申请公布日期 2001.04.06
申请号 JP19990268866 申请日期 1999.09.22
申请人 SANYO ELECTRIC CO LTD 发明人 ISHIZUKA YOSHIYUKI
分类号 G11C11/41;G11C11/401;G11C11/407;(IPC1-7):G11C11/407 主分类号 G11C11/41
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