EMBEDDED COMPUTER SYSTEM AND METHOD WITH DUAL WATCHDOG TIMER

摘要

Dual watchdog timer [Fig.2] and method for recovering a computer system in the event of a problem. A first counter (21) is advanced from an initial value toward a final value, and a first recovery signal is delivered if the final value is reached. If the system is functioning properly, the first counter is reset periodically to the initial value so that the first recovery signal will not be delivered. A second counter (23) is advanced from an initial value toward a second value in response to the first recovery signal, and a second recovery signal is delivered if the second value is reached. The second counter will not reach the second value and deliver the second recovery signal if proper operation of the system is restored before the second count is reached. The recovery signals are utilized as a software interrupt and/or as a hardware reset signal.