发明名称 ARRANGEMENT TO REDUCE COUPLING NOISE BETWEEN BITLINES
摘要 <p>An integrated circuit comprising first and second bitline pairs 410 and 420 is described. The bitline paths of a bitline pair are on different bitline levels. The bitline paths of the first and second bitline pairs which are on different bitline levels are adjacent to each other. The first bitline pair comprises m vertical-horizontal twists 440, where m is a whole number ≥ 1, and the second bitline pair comprises n vertical-horizontal twists 460 and 461, where n is a whole number ≠ m. The vertical-horizontal twists transform coupling noise into common mode noise.</p>
申请公布号 WO2001024188(A1) 申请公布日期 2001.04.05
申请号 US2000024918 申请日期 2000.09.12
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