| 摘要 |
A frequency generating circuit comprises a first, fine PLL frequency synthesiser circuit (FS2) which consumes a low current and is slow to settle, a second, coarse PLL frequency synthesiser circuit (FS1) which consumes a high current and is fast to settle, and a signal combining circuit (36) for additively combining the outputs of the first and second frequency synthesiser circuits to provide a final output frequency. The first frequency synthesiser circuit is energised sufficiently in advance of the second frequency synthesiser circuit that both achieve lock substantially simultaneously. The overall current consumed is less than would be consumed if a single PLL frequency synthesiser is used to generate the final frequency.
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