| 摘要 |
A second processor is accessed by a binary access signal (trs) which is sampled with sample slopes (fl1-fl3) of the clock signal (tqq) of the second processor. When the first processor has a higher clock frequency than the second processor then a new binary access signal (trs*) is generated using a chip select signal (csl) of the matching logic. The access state of the new signal lies in the region of at least one sampling slope (fl2) of the clock signal (tqq).
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