TWISTED BITLINES ARCHITECTURES

摘要

An integrated circuit comprising first and second adjacent signal line pairs (310 and 320) is described. The signal line pairs comprise diagonal signal paths (311p, 312p; 321p and 322p) with directional changes (335). The first signal line pair comprises m twists (340), where m is a whole number >/= 1, and the second signal line pair comprises n twists (360 and 361), where n is a whole number ≠ m.