发明名称 |
A floating point instruction set architecture and implementation |
摘要 |
<p>Processor and co-processor elements, structured to execute a floating-point instruction set architecture, as described. Examples are given of loading and storing double precision words and/or pairs of single precision words between a floating-point co-processor and memory, as well as storing the Boolean result of comparing two floating-point numbers in a floating-point unit in an integer register in a CPU. <IMAGE></p> |
申请公布号 |
EP1089165(A2) |
申请公布日期 |
2001.04.04 |
申请号 |
EP20000308582 |
申请日期 |
2000.09.29 |
申请人 |
HITACHI, LTD. |
发明人 |
KRISHNAN, SIVARAM;DEBBAGE, MARK;ROY, KANAD;ARAKAWA, FUMIO;STURGES, ANDY CRAIG;FARRALL, GLENN ASHLEY |
分类号 |
G06F7/00;G06F9/30;G06F9/312;G06F9/38;(IPC1-7):G06F9/312;G06F9/318;G06F9/305 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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