发明名称 COMPLEX PHASE-LOCKED LOOP DEMODULATOR FOR LOW-IF AND ZERO-IFRADIO RECEIVERS
摘要 A digital demodulator which coherently demodulates a low-IF or zero-IF compl ex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provi de independent phase/frequency and amplitude outputs. The CPLL exhibits in firs t order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2 nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low F M modulation indexes whereby the incoming frequency drift may be larger than t he frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.
申请公布号 CA2284948(A1) 申请公布日期 2001.04.04
申请号 CA19992284948 申请日期 1999.10.04
申请人 PHILSAR ELECTRONICS INC. 发明人 BIRKETT, NEIL;RILEY, THOMAS;FILIOL, NORM
分类号 H03D3/24;H04L27/38;(IPC1-7):H04L27/152 主分类号 H03D3/24
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