发明名称 Self-aligned eetching process
摘要 The invention describes a self-aligned etching process. A conductive layer and a first insulating layer are formed on a substrate in sequence, and then the conductive layer and the first insulating layer are patterned to form a plurality of stacks on desired regions. Subsequently, spacers are formed on sidewalls of each stack, and a stop layer is then formed on the substrate. A second insulating layer is formed on the substrate and is planarized. Portions of the second insulating layer are removed to form a plurality of openings and to expose portions of the stop layer located between spacers. The exposed stop layer is removed.
申请公布号 US6211091(B1) 申请公布日期 2001.04.03
申请号 US19990373318 申请日期 1999.08.12
申请人 WORLDWIDE SEMICONDUCTOR MFG. CORP. 发明人 LIEN WAN-YIH;CHERNG MENG-JAW
分类号 H01L21/02;H01L21/311;H01L21/60;H01L21/768;H01L21/8242;H01L27/108;(IPC1-7):H01L21/305 主分类号 H01L21/02
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