PHASE REGULATOR FOR OUTPUT CLOCK

摘要

PURPOSE: A phase regulator for an output clock is provided to maximize a clock access time and a data output hold time spec-margin in each CAS latent time mode by regulating a phase of an output clock according to CAS latent time. CONSTITUTION: A phase regulator includes an input buffer(22) and an output driver(24) that buffer an input clock(CLK) of an input pad(21) and output an output clock(QCLK). A delay MUC(23) has a variable delay level according to CAS latent time between the input buffer(22) and the output driver(24). Thereby, the phase regulator maximizes a clock access time and a data output hold time spec-margin in each CAS latent time mode by setting a phase of an output clock to an optimum position.