发明名称 |
Semiconductor memory device with multiple sub-arrays of different sizes |
摘要 |
A semiconductor memory device includes a memory cell array divided into a plurality of sub-arrays. The number of memory cells per bit line in at least one of the sub-arrays differs from the number of memory cells per bit line in other sub-arrays. When the sense amplifiers can accommodate a bit line loading of (2M+2M/N) memory cells per bit line, the size and bit line loading of one of more of the sub-arrays can be increased. This can provide sub-arrays of different sizes and can reduce the number of the sub-arrays and the number of the sense amplifier regions. Accordingly, the chip efficiency is improved. Maximum current for sensing during simultaneous accesses of multiple arrays can access two sub-arrays with different bit line loadings and avoid simultaneously accessing two sub-arrays having high bit-line loadings.
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申请公布号 |
US6212121(B1) |
申请公布日期 |
2001.04.03 |
申请号 |
US19990451466 |
申请日期 |
1999.11.30 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
RYU HOON;HWANG MOON-CHAN;JEON JUN-YOUNG |
分类号 |
G11C8/12;(IPC1-7):G11C8/00 |
主分类号 |
G11C8/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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