| 摘要 |
A method and apparatus are provided for performing a Hadamard transform oper ation. The basic building block of the apparatus is an FHT engine comprising a subtractor (2) for subtracting an input symbol from a delayed processed symbol, first multiplexer (4) for providing either the difference of the delayed processed symbol and the inpu t symbol or the first input symbol, a memory element for storing the output of the first multiplexer (4) as the delayed processed symbol, a s ummer (6) for adding the input symbol to the delayed pro cessed symbol and a second multiplexer (8) for providing either the sum of the inpu t symbol and the delayed processed symbol or the delayed processed symbol as an output. This basic engine is designed to work in con junction with a variety of different memory configuratio ns. The engines can then be placed in series to perform a Hadamard transform of all defined orders. In addition, two methods of optimizing the use of memory resources are described. One involves the optimal configuration o f the memory elements and the second involves truncation . Also, provided is a method and apparatus for performing the transform on sam ples received as a serial bit stream.
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