发明名称 Method to verify the integrity of the decoding circuits of a memory
摘要 A method for testing decoding circuits in a memory including a matrix of storage cells includes writing the same first word in all the storage cells, and then writing second words in the matrix such that each row and each column has at least one stored second word. The second words are different from the first words. If several second words are written in the same row or in the same column, then the second words are different from one another. Reading all the words in the memory permits verification of the integrity of the decoding circuits, and reduces the testing time of the memory.
申请公布号 US6212112(B1) 申请公布日期 2001.04.03
申请号 US19990452446 申请日期 1999.12.02
申请人 STMICROELECTRONICS S.A. 发明人 NAURA DAVID;MONCADA FREDERIC
分类号 G11C29/02;G11C29/10;(IPC1-7):G11C7/00;G01R31/28 主分类号 G11C29/02
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