| 摘要 |
A method of fabricating an integrated circuit includes forming a gate stack upon an active region of a substrate which includes a gate dielectric, a polysilicon gate conductor and a polysilicon consumption metal layer portion. The polysilicon consumption metal layer portion is then reacted with the polysilicon gate conductor to form a high conductivity gate conductor (silicide). In one embodiment, the polysilicon gate conductor is fully consumed. In another embodiment, the polysilicon gate conductor is substantially consumed but a portion of the polysilicon gate conductor adjacent the gate dielectric remains. In forming such a gate structure, a gate dielectric layer is first formed and a polysilicon gate layer is formed upon the gate dielectric layer. A polysilicon consumption metal layer is then formed upon the polysilicon gate layer. The surface is then patterned mask so that the location of the gate structures is protected. The substrate is then anisotropically etched to form the gate structures. At this point, an optional rapid thermal annealing step may be performed to partially react the polysilicon consumption metal layer portion with the polysilicon gate conductor. Spacers, lightly doped drain regions and source and drain regions are then formed. Next, a silicidation metal layer is formed and the structure is reacted in a rapid thermal annealing step to form silicidation layers in the source and drain regions and to complete reaction of the polysilicon consumption metal layer portion with the gate conductor. Subsequently, the transistors may be interconnected to form an integrated circuit.
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