| 摘要 |
An object of the present invention is to enlarge voltage amplitude of bit lines at a short time when reading out data from memory cells. A semiconductor memory device according to the present invention comprises an initialization circuit 1 constituted of a plurality of memory cells MC1, MC2-MCn, precharge transistors Q2 and Q3, and an equalizing transistor Q1, and a load circuit constituted of load transistors Q4 and Q5. When reading out data from the memory cells MC1-MCn, supply of electric charge to bit lines BLA and BLB by the load transistors Q4 and Q5is temporarily interrupted. Because of this, it is possible to enlarge the voltage amplitude of the bit lines BLA and BLB from the power supply voltage VDD as compared with the case of always supplying the electric charge to the bit lines BLA and BLB from the power supply voltage VDD. Furthermore, the semiconductor memory device of the present invention interrupts the supply of the electric charge to the bit lines BLA and BLB during writing to the memory cells MC1-MCn. Because of this, it is possible to reduce the current consumption, thereby improving write margin.
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