发明名称 |
Methods and arrangements for reducing stress and preventing cracking in a silicide layer |
摘要 |
Methods and arrangements that increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device are provided. The methods and arrangements effectively prevent cracks from developing within a tungsten suicide layer that is part of a control gate structure within a non-volatile memory cell. Cracks within the tungsten silicide layer can affect the performance of the memory cell by increasing the resistance of the control gate configuration. The methods and arrangements prevent cracking of the tungsten silicide layer by minimizing the relative difference between temperatures associated with the deposition of the tungsten suicide layer and deposition of a subsequent overlying cap layer.
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申请公布号 |
US6211074(B1) |
申请公布日期 |
2001.04.03 |
申请号 |
US19980076584 |
申请日期 |
1998.05.12 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
HUANG RICHARD J.;MORALES GUARIONEX |
分类号 |
H01L21/3205;H01L21/8247;H01L27/115;(IPC1-7):H01L21/476;H01L21/336 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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