| 摘要 |
A double-data rate (DDR) memory device is disclosed that can be configured for testing on an ordinary memory tester. The DDR memory may include a DDR input circuit (102), a single data rate input circuit (104), a word line control circuit (106), a bit line control circuit (108), and a memory cell array (110). Normal write operations may be performed by selecting the DDR input circuit (102). Test write operations may be performed by selecting the SDR input circuit (104). Such an arrangement can enable a DDR memory device to be tested in an ordinary SDR memory tester.
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