SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To provide a latch type sense amplifier in which high speed can be achieved while reducing noise being applied to a signal voltage through capacitive coupling of a transistor when a latch activation signal is varied. SOLUTION: First and second transfer switches TG1, TG2 are inserted, respectively, between the input terminal A1 of a latch circuit 1 and a terminal SA1 receiving a voltage produced by converting a current flowing through a digit line connected with a memory cell and between the input terminal A2 of the latch circuit 1 and a terminal SA2 receiving a reference voltage from a reference voltage generating circuit. The sense amplifier circuit comprises complementary transfer switches of NMOS and PMOS transistors having gates receiving a sense amplifier latch activation signal BSAL and a complementary signal TSAL therof. The gate-drain capacitances C0N and C0P (gate-source capacitance) of the NMOS and PMOS transistors are equalized with each other and the rising and falling times of signals BSAL and TSAL having reverse phase are equalized.