发明名称 MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To improve the load and the using efficiency of a CPU by cutting off a bus line between storing means, which has to directly transfer data, from the CPU so as to execute data-transferring operation independent from data- accessing operation by the CPU. SOLUTION: A data bus consists of a sub-data bus 46 restrictively connecting specific storing means 1a and 1b and the other main data bus 24. In accordance with the time of requiring direct data transfer, the bus 46 is electrically cut off from a CPU 22, and an access signal 56 consisting of an address signal and a control signal is respectively supplied to the means 1a and 1b. The bus 24 and the bus 46 are connected through a buffer means 2 such as a bi- directional buffer. The access signal 56 sent from the CPU 22 is respectively supplied to the means 1a and 1b through a memory control means 3.
申请公布号 JP2001084173(A) 申请公布日期 2001.03.30
申请号 JP19990255696 申请日期 1999.09.09
申请人 DIGITAL ELECTRONICS CORP 发明人 TAKAMOTO TAKASHI
分类号 G06F12/06;G06F12/00;G06F13/16;(IPC1-7):G06F12/06 主分类号 G06F12/06
代理机构 代理人
主权项
地址