| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory suitable for mixed mounting of logic in which the working frequency can be increased while reducing power consumption. SOLUTION: Pairs of read data line (IOR0-IOR31), write data lines (IOW0- IOW31) and spare read data lines (SIR), spare write data lines (SIW) are arranged across a memory cell array while extending in the column direction. A spare bit is repaired by replacing the pairs of data line. A column redundancy control circuit (CRC) alters the timing for outputting the spare decision results when a transition is made between a data write mode and a data read mode. |
