发明名称 INFORMATION PROCESSOR
摘要 PROBLEM TO BE SOLVED: To speedily process an extension instruction by dividing arithmetic units by the type of arithmetic operations, providing a plurality of extension arithmetic units and operating them in parallel. SOLUTION: An instruction decoder 107 detects an instruction to be an extension instruction and a general purpose part sequencer 112 asserts an REQ signal 122. An expansion instruction decoder 111 informs a first extension unit sequencer 116 that the first-kind extension instruction is issued. The sequencer 116 issues a control signal and asserts an ACK signal 123 through an ACK signal generation logic 130. In accordance with the control of the first extension unit control logic 119, the first extension arithmetic unit executes an instruction. Further, the decoder 111 informs the second extension unit sequencer 125 that the second kind extension instruction is issued. In accordance with the control of the logic 128, the second extension arithmetic unit executes the instruction.
申请公布号 JP2001084143(A) 申请公布日期 2001.03.30
申请号 JP19990257539 申请日期 1999.09.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TSURUTA HIDEYO
分类号 G06F9/38;G06F9/30;G06F9/308;G06F15/16;G06F15/80;(IPC1-7):G06F9/38 主分类号 G06F9/38
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