| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of requests for transfer on a bus line, and to attain an efficient memory access. SOLUTION: A memory clear signal for instructing the reading of a memory 7 and the writing of zero data in the same address afterwards is added to a local bus 8 connecting a memory controller 2 with each bus master 4 and 5. Then, a byte enable signal is used as a 4 byte clear enable signal at the time of memory read clear, and when memory read clear is requested, the memory controller 2 operates for the writing of zero data in the same address according to the 4 byte clear enable signal when the memory read clear is requested after the end of the read.
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