PARALLEL COMPUTER ARCHITECTURE, AND INFORMATION PROCESSING UNIT USING THE ARCHITECTURE

摘要

A distributed-memory computer architecture is provided that is capable of extremely high-speed processing. A computer system (10) comprises a CPU modu le (12), a plurality of memory modules (14) each provided with a MPU (36) and a RAM core (34), and a plurality of buses (24) for connections between the CPU module and the memory modules and between the memory modules. The memory modules operate according to instructions given by the CPU (12). A space ID is given to a series of data associated with one another. Each memory module manages at least such space IDs, logical addresses of the series of data portions managed by the memory itself, and a table containing the size of th e series of data. Each memory module also decides whether the series of data portions managed by the memory itself is involved in a received instruction, and processes the data stored in the RAM core.