发明名称 METHOD AND ARRANGEMENT FOR DIELECTRIC INTEGRITY TESTING
摘要 <p>A semiconductor testing process effectively determines the integrity of a large capacitive structure (CL, CR) buried within an integrated circuit. According to one example embodiment, a process of testing the oxide integrity of a circuit involves selecting a large gate oxide structure or structures that can be isolated from leakage paths. The dielectric integrity of the structure is tested by stressing the structure via voltage settings, comparable to a supply voltage, across its two terminals. The structure is connected to a current-sensitive node (218) in the integrated circuit across the two terminals. Other circuits connected to the current-sensitive node (218) are shut off so that the current-sensitive node (218) should be an island relative to other current paths. The leakage current at the current-sensitive node is then measured and compared with a reference level. From the measurements and comparison, a quality factor indicative of the dielectric integrity in the structure is determined.</p>
申请公布号 WO2001022105(A1) 申请公布日期 2001.03.29
申请号 US2000025920 申请日期 2000.09.22
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