| 摘要 |
<p>A timing circuit (130) produces a memory clock signal. An address buffer circuit (112) receives and stores a first address in a first latch (340A) and a second address in a second latch (340B) asynchronously with respect to the clock signal. A memory control circuit (114) associated with an array of memory cells (120) accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.</p> |
