| 摘要 |
The invention relates to a data processing device having a clock recovery system for locking a clock frequency to time stamps (PCR) of an incoming data stream, e.g. MPEG. It is proposed to use a free running clock (20) that generates a reference frequency (FREF) from which a desired locked clock frequency is synthesized (25,35) under control of a processing unit (24,34) that compares (241,341) the locked clock frequency to the time stamps (PCR). MPEG audio and video processing clock frequencies are synthesized (25,35) from a free running reference frequency (FREF) and locked to the MPEG time base on basis of time stamps (PCR) provided in the MPEG data stream. Other sub-systems (23,23') run on frequencies that are not locked to the time base, e.g. simple multiples (22,22') of the free running reference frequency (FREF). Audio and video D/A converters (28,38) run on the same clock frequency, or on two different clock frequencies having a simple mutual ratio that are synthesized from the free running reference frequency (FREF) without locking to the time base. Sample rate converters (27,37) are present in the signal path to adjust the output signal of a processing unit (26,36) to the input of the D/A converter (28,38). Time base regulation for audio (24,25,261) and video (34,35,361) is performed independently.
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