发明名称 PHASE-LOCKED LOOP
摘要 For prompt restoration of a PLL being in inactive state due to an abnormal oscillation of a voltage-controlled oscillator, it is checked that a frequen cy divider (4) provides a comparison signal (fc). If no comparison signal (fc) is detected, a phase comparator (1) is forced to decrease its output level temporarily to decrease the oscillating frequency of the voltage-controlled oscillator (3). The method is suitable for generation of a wide range of sampling clocks to be used for the digital processing of analog video signal s.
申请公布号 CA2351759(A1) 申请公布日期 2001.03.29
申请号 CA20002351759 申请日期 2000.08.23
申请人 FUJITSU GENERAL LIMITED 发明人 KIMURA, TAKUSHI;NAKAJIMA, MASAMICHI
分类号 H03L7/095;H03L7/10;H03L7/18;(IPC1-7):H03L7/083 主分类号 H03L7/095
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