| 摘要 |
FIFO storage and shared buffer switching device for connection networks in ATM technology comprising a plurality of input sections (Interface_ini) on which ATM input cell flows (Cell_ini(p_in:1)) and associated service signals (Cell_en_ini, Cell_str_ini, Cell_rout_tagi, Ck_ini) transit, and a plurality of output sections (Interface_outj) on which respective ATM output cell flows (Out_sectj(p_out:1)) and respective associated service signals (Cell_en_outj, Cell_str_outj, Cell_avj, En_outj and Ck_outj) transit. The device comprises a memory array (Mem_array) set up by a series of memory sections assigned to memorize the ATM cells which arrive at said input sections and in which the enables for the transmission of the cells are arranged according to priority queues, each one corresponding to a different output. So inside the above-said memory array (Mem_array) several FIFOs are realized, one for each output with variable depths and containing queues of ATM cells. |
