| 摘要 |
Pipelined processing unit (100) with an instruction sequencer (101) having a random access memory (516) containing very long instruction words (VLIWS) and with n functional units capable of executing n operations in parallel. Each VLIW is composed of a plurality of short instruction words (SIWS) loaded and concatenated in each address or entry of the VLIW memory (VIM) (516) to form an indirect VLIW (iVLIW). Each SIW corresponds to a unique type of instruction associated with a unique functional unit. iVLIWs are executed via the executive-VLIW (XV) instruction. The XV1 instruction, by use of a mask field which can be modified each time the XVI instruction is executed, specifies which functional units are enabled or disabled during execution of the iVLIW. The VIM (516) can be further partitioned into separate memories (520, 522, 524, 526, 528) each associated with a function decode and execute unit (540, 542, 544, 546, 548). A second XV instruction, XV2, can independently address each functional units portion of the VIM (516).
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