| 摘要 |
A combination mode of a transfer source and a transfer destination for the data transfer is previously defined depending on a value of the resource select information of a control register (CHCRn). An address comparator circuit (SACn, DACn) has a judging logic specified by the defined contents and detects, depending on such logical structure, the data transfer control disable address error by a data transfer controller (8) on the basis of such logical structure, in accordance with the resource select information and the transfer source address, transfer destination address of the address register (SARn, DARn). Since the data transfer is started only when the resource select information matches with the setting information of both address registers, high reliability can be assured for memory protection in the data transfer operation by the data transfer controller.
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