发明名称 Complementary clock pulse generator using CMOS technology
摘要 A first transmit switch (2) contains an input (23), an output and two control terminals (21,22) for coupling the input and output terminals, when the input clock pulse signal (Clkin) has reached the first control terminal (21), and the inverted clock pulse signal from the first inverter (11) has reached the second control terminal (22). A second transmit switch (3) has two control terminals (31,32) for coupling its input (33) and output terminal (34) under similar conditions as for the first switch. The synonymous clock pulse signals (Clk) are obtained from the first switch output terminal, and the counterphase clock pulse signals (/Clk) are derived from the second switch output terminal.
申请公布号 DE19624270(A1) 申请公布日期 1997.07.10
申请号 DE19961024270 申请日期 1996.06.18
申请人 LG SEMICON CO., LTD., CHEONGJU, KR 发明人 KIM, DAE-JEONG, SEOUL/SOUL, KR
分类号 H03K3/00;H03K5/151;(IPC1-7):H03K5/151;H03F3/26 主分类号 H03K3/00
代理机构 代理人
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