Speicherzellenanordnung und Verfahren zu deren Herstellung

摘要

In a memory cell arrangement which includes vertical MOS transistors as the memory cells, information is stored by different threshold voltages of the transistors. Dopant regions are formed for an information state by angular implantation or diffusion in the upper part of the channel region. The lower part of the channel region is consequently covered by an etching residue (9') which is produced by a masked spacer etching. The arrangement can be produced with a surface requirement of 2 F<2> (F being the minimum structural size) per memory cell.