发明名称 Voltage tolerant buffer
摘要 The present invention provides a buffer for coupling circuitry operating at a low voltage to circuitry operating a high voltage, and vice versa. The buffer outputs signals in a range between the low voltage and a ground voltage lower than the low voltage, and maintains appropriate bias of a semiconductor junction in the buffer using the high voltage. For example, the high voltage can be applied to the body of an output stage pull-up PFET of the buffer to maintain reverse bias between the body and drain of the PFET even when signals at the high voltage are placed on the drain of the PFET by other circuitry. Some embodiments of the present invention include a voltage translator to translate signals output from circuitry operating at the low voltage into a control signal at either the ground voltage or the high voltage. The high voltage of the control signal is beneficial for turning OFF an output stage transistor of the buffer even in the presence of signals at the high voltage on an output of the buffer. The roles of the low and high voltage can also be reversed, for example, by using a ground voltage higher than the high voltage.
申请公布号 US6208167(B1) 申请公布日期 2001.03.27
申请号 US19970974073 申请日期 1997.11.19
申请人 S3 INCORPORATED 发明人 RANJAN NALINI;SRIBHASHYAM SARATHY
分类号 H03K3/356;H03K19/0185;(IPC1-7):H03K19/017 主分类号 H03K3/356
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