| 摘要 |
A memory device, which writes data upon receiving a write command and reads data upon receiving a read command, comprises: a data input/output circuit for inputting and outputting the data in synchronization with first and second edges of a clock; and a cell array including a plurality of memory cells which store the data are. The memory device includes two sets of data bus lines connected to the cell array via column gates, a serial/parallel converter for inputting and outputting first and second write data, and two write amplifiers for driving the two data bus lines in accordance with the first and the second write data from the serial/parallel converter. The write amplifiers are activated in a write enabled state and the write amplifier is deactivated in response to a data mask signal despite being in the write enable state. The memory device has a column decoder which selects the column gate, and is inhibited the activation in response to the data mask signal. Therefore, the write-interrupt-read operation can appropriately be performed for a memory device which is compatible with the double data rate.
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