| 摘要 |
A programmable logic device, such as a digital signal processor (DSP) (130), having a Chien search unit (116) is disclosed. The Chien search unit (116) is arranged to perform finite field arithmetic functions useful in identifying roots of a polynomial, as is useful in Reed-Solomon decoding, particularly, after the execution of a Euclidean array function. Galois field multipliers (306) perform finite field multiplication of coefficient values (LAMBD) and powers of symbol values (alpha); the products of such multiplications are written into the coefficient register (304) for use in connection with the next symbol value. Finite field adders (308, 310; 318, 320) produce a final sum that is interrogated by zero detection circuitry (206) to determine whether a root is presented by the current symbol value. The provision of a Chien search execution unit (116) provides important efficiency so as to enable programmable logic devices, such as digital signal processors (130) and microprocessors to effect Reed-Solomon decoding.
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