| 摘要 |
A method for fabricating a metal interconnect involves forming a first dielectric layer on the substrate having metal lines formed thereon, wherein the top surface of the first dielectric layer is lower than that of the metal line. As a result, the top surface and a part of the sidewall of the metal line are exposed. A spacer is then formed on the exposed sidewall of the metal line. A second dielectric layer is formed on the substrate, wherein the spacer has different etching selectivity from the second dielectric layer. With the spacer serving as an etching stop layer, a via opening is formed in the second dielectric layer, while the via opening is filled with a metal plug to form a via plug.
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