| 摘要 |
A delay cell comprises a fast delay stage including a differential amplifier for connection to a differential input. A slow delay stage includes a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount. A current source develops a bias current. A current switch is connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage. An output circuit is connected to the fast and slow delay stages for developing a differential output delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current.
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