| 摘要 |
The transmitting device latches the time of the absolute clock (IEEE P1394 CTR (cycle time register)) when the V-sync signal of the video signal block is transmitted, adds to the latched time a predetermined delay time equivalent to the sum of the time required for the transmitting device to process the video signal block and the time required for the transmittance; and transmits the resulting sum value together with the video signal block. The receiver extracts the sum value and produces the V-sync signal delayed by said predetermined delay time. <IMAGE> |
