发明名称 Synchronous delay generator
摘要 A method for generating a variable delay of a signal (28), including: providing a clock (50) indicating a sequence of sample times at regular intervals and receiving a sequence of input samples (41) representing input values of the signal at respective sample times indicated by the clock. The method further includes determining the delay (40, 46) with a temporal resolution substantially finer than the clock interval to be applied to the signal at each of the respective sample times. For each of the sample times, responsive to the respectively-determined delay, one or more of the input samples are processed so as to generate a corresponding output sample (43) representing a delayed output value of the signal at the sample time.
申请公布号 AU7096600(A) 申请公布日期 2001.03.26
申请号 AU20000070966 申请日期 2000.08.30
申请人 QUALCOMM INCORPORATED 发明人 MAURIZIO DI VEROLI;AYAL BAR-DAVID
分类号 H04B7/212;H04L7/00;H04L7/02 主分类号 H04B7/212
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