| 摘要 |
A method and apparatus for synchronizing output data and data strobe signals uses internal interleaved clock signals in a double data rate (DDR) DRAM that are synchronized with an external clock. A delay-locked loop internal to the DDR DRAM is locked to an external clock signal and generates the internal interleaved clock signals. The internal interleaved clock signals are delay matched with the external clock signal as they propagate through timing circuitry coupled to latency and burst length selection signals. A data strobe signal is generated using clock signals from the delay-locked loop and is synchronized with the internal interleaved clock signals. The data strobe signal and the data are coupled via paths having comparable numbers and types of delay elements to provide output data and data strobe signals having predetermined delay relationships with the external clock signal. |
